Clock driver with duty cycle correction
Number of patents in Portfolio can not be more than 2000
United States of America
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Jan 28, 2025
Grant Date -
Nov 14, 2024
app pub date -
May 11, 2023
filing date -
May 11, 2023
priority date (Note) -
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status (Latency Note)
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Abstract
A clock driver with duty cycle correction includes a first driver circuit, a second driver circuit, and a correction logic circuit. The first driver circuit performs duty cycle correction on a clock input signal and has parameters selected for a first frequency range of the clock input signal. The second driver circuit is nested with the first driver circuit and performs duty cycle correction on the clock input signal with parameters selected for a second frequency range of the clock input signal lower than the first frequency range. The correction logic circuit provides correction signals to a selected one of the first driver circuit and the second driver circuit. The clock driver provides a duty cycle corrected clock signal from the selected one of the first driver circuit and the second driver circuit based on a selected frequency range of the clock input signal.
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