Three dimensional integrated circuit and fabrication thereof
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
Jan 28, 2025
Grant Date -
Nov 23, 2023
app pub date -
Jul 31, 2023
filing date -
Jul 31, 2023
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully