Layout for dual in-line memory to support 128-byte cache line processor
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United States of America
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Jan 28, 2025
Grant Date -
Apr 27, 2023
app pub date -
Oct 24, 2022
filing date -
Oct 24, 2022
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Abstract
A memory stick configured for use with a processor in a computer is provided. The memory stick includes a printed circuit board with first and second sides, each of the first and second sides including eighteen memory chips, each of the memory chips being an ×8 DRAM chip; the eighteen memory chips being distributed into first, second, third and fourth rows, the first row and the second row being on a left half of the printed circuit board and the third and fourth row being on a right half of the printed circuit board; and the printed circuit board including at least 400 pins including at least 16 pins for ECC bits and at least 128 pins for data bits; wherein at least the memory chips and the 128 pins for data bits establish a 128-bit data width to communicate.
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