Test circuit and method for reading data from a memory device during memory dump
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United States of America
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Jan 28, 2025
Grant Date -
Oct 19, 2023
app pub date -
Mar 31, 2023
filing date -
Mar 31, 2023
priority date (Note) -
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Abstract
A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.
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