Fast two-sided corrective read operation in a memory device
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United States of America
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Jan 28, 2025
Grant Date -
Jun 8, 2023
app pub date -
Oct 20, 2022
filing date -
Oct 20, 2022
priority date (Note) -
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Abstract
A memory device includes an array of memory cells associated with wordlines and control logic. The control logic performs operations that cause a corrective read operation to be performed at a selected memory cell. The operations include: causing a first voltage to be applied to a first wordline associated with the selected memory cell; causing a second voltage, having a lower magnitude than the first voltage, to be applied to wordlines adjacent to the first wordline and associated with each of two neighbor memory cells of the selected memory cell; in response to determining that current flows through the two neighbor memory cells and the selected memory cell between a bitline and a source line of the array, identifying a first corrective read voltage; and causing the first corrective read voltage to be applied to the first wordline during a read operation for the selected memory cell.
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