Page buffer circuit and memory device including the same
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United States of America
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Jan 28, 2025
Grant Date -
May 11, 2023
app pub date -
Oct 13, 2022
filing date -
Oct 13, 2022
priority date (Note) -
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Abstract
A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.
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