Semiconductor memory device
Number of patents in Portfolio can not be more than 2000
United States of America
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Jan 28, 2025
Grant Date -
Feb 8, 2024
app pub date -
Mar 1, 2023
filing date -
Mar 1, 2023
priority date (Note) -
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Abstract
A semiconductor memory device includes a first memory pillar and a sequencer. The first memory pillar is sandwiched between a first word line and a second word line, sandwiched between a third word line and a fourth word line, sandwiched between a fifth word line and a sixth word line, includes a first memory cell facing the first word line, a second memory cell facing the second word line, a third memory cell facing the third word line, a fourth memory cell facing the fourth word line, a fifth memory cell facing the fifth word line and a sixth memory cell facing the sixth word line. The sequencer executes an erase operation on the first to sixth memory cells to enable execution of a primary write operation for the first memory cell and a primary write operation for the second memory cell at different timings.
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