Semiconductor memory device
Number of patents in Portfolio can not be more than 2000
United States of America
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Jan 28, 2025
Grant Date -
Mar 21, 2024
app pub date -
Mar 2, 2023
filing date -
Mar 2, 2023
priority date (Note) -
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Abstract
A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.
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