Semiconductor memory device having memory chip bonded to a CMOS chip including a peripheral circuit

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United States of America

PATENT NO 12211544
APP PUB NO 20230402087A1
SERIAL NO

18239140

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Abstract

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A memory device includes a first memory cell provided above a substrate; a first bit line coupled to the first memory cell and extending in a first direction; a first sense amplifier configured to sense a voltage of the first bit line; a second memory cell provided above the substrate; a second bit line adjacent to the first bit line and extending in the first direction, the second bit line being coupled to the second memory cell; a second sense amplifier configured to sense a voltage of the second bit line; and a third memory cell provided above the substrate. A third bit line not adjacent to the second bit line extends in the first direction, and is coupled to the third memory cell; and a third sense amplifier is configured to sense a voltage of the third bit line. The first and second sense amplifiers belong to a first sense amplifier group, are adjacent to each other and are arranged in a second direction intersecting the first direction. The third sense amplifier belongs to a second sense amplifier group. The first and second sense amplifier groups are adjacent to each other and are arranged in the first direction.

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Patent Owner(s)

  • KIOXIA CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Maejima, Hiroshi Tokyo, JP 246 4455

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