CMUT-on-CMOS ultrasonic transducer by bonding active wafers and manufacturing method thereof
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United States of America
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Jan 28, 2025
Grant Date -
Sep 28, 2023
app pub date -
Nov 24, 2022
filing date -
Nov 24, 2022
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present invention provides a new architecture of system-on-chip ultrasonic transducer array. It is based on fusion bond of two active wafers which have prefabricated CMOS integrated circuits and CMUT structures; precise thin-down of one wafer to form CMUT monocrystalline silicon membrane; and then to vertically connect CMUT array to CMOS IC layers underneath. This architecture can realize a high-density CMUT array with multiple layers of CMOS devices, such as all supporting CMOS ICs, to achieve a SOC solution. The present invention further provides a manufacturing method for above-mentioned SOC CMUT approach, and this manufacturing process can be realized in both 8 inch and 12-inch wafer manufacturing fabs. The disclosed manufacturing processes are more compatible with existing CMOS process flow, more cost-competitive for mass production.
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International Classification(s)
- 2022 Application Filing Year
- B06B Class
- 253 Applications Filed
- 80 Patents Issued To-Date
- 31.63 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- B06B Class
- 0 % this patent is cited more than
- < 1 Age
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