Methods and apparatus to reduce inter-stage gain errors in analog-to-digital converters
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 21, 2025
Grant Date -
Feb 29, 2024
app pub date -
Aug 30, 2022
filing date -
Aug 30, 2022
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.
First Claim
Other Claims data not available
Family
International Classification(s)
- 2022 Application Filing Year
- H03M Class
- 1388 Applications Filed
- 948 Patents Issued To-Date
- 68.30 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H03M Class
- 0 % this patent is cited more than
- < 1 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 3.5 Year Payment | $1600.00 | $800.00 | $400.00 | Jul 21, 2028 |
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jul 21, 2032 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jul 21, 2036 |