Variable resolution digital equalization

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United States of America Patent

PATENT NO 12206423
APP PUB NO 20230253974A1
SERIAL NO

18092564

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Abstract

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A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INCCALIFORNIA USA CALIFORNIA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dyer, Kenneth C Pleasanton, US 31 155
Hossain, Masum Edmonton, CA 64 667
Nguyen, Nhat San Jose, US 19 119
Tangirala, Shankar Fremont, US 7 15

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