IC with delay-locked loop with widened lock range
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United States of America Patent
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Jan 21, 2025
Grant Date -
Jun 13, 2024
app pub date -
Feb 21, 2024
filing date -
Dec 31, 2021
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Abstract
An integrated circuit (IC) features a delay-locked loop (DLL) with a DLL signal input. The DLL comprises a delay line with multiple delay stages, a gater with clock input, and a phase-frequency detector (PFD). The delay line's signal input is linked to the DLL signal input, while the gater's inputs are connected to phase outputs of the delay line. The gater's clock input is tied to the DLL signal input, and its outputs feed into the PFD inputs. The PFD generates outputs that are used by a loop filter to control the speed of the delay line.
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