Duty cycle monitoring method and apparatus for memory interface
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United States of America Patent
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Jan 21, 2025
Grant Date -
Jun 13, 2024
app pub date -
Jul 18, 2023
filing date -
Dec 8, 2022
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Abstract
Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
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