Delay-compensating power management circuit

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United States of America Patent

PATENT NO 12206364
APP PUB NO 20240136979A1
SERIAL NO

18402102

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Abstract

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A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g., amplitude clipping) during amplification of the analog signal.

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Patent Owner(s)

Patent OwnerAddress
QORVO US INC7628 THORNDIKE ROAD GREENSBORO NC 27409

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Khlat, Nadim Cugnaux, FR 547 12808

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