Semiconductor device with deep trench isolation mask layout

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United States of America Patent

PATENT NO 12206002
APP PUB NO 20220384595A1
SERIAL NO

17560465

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Abstract

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A deep trench layout implementation for a semiconductor device is provided. The semiconductor device includes an isolation film with a shallow depth, an active area, and a gate electrode formed in a substrate; a deep trench isolation surrounding the gate electrode and having one or more trench corners; and a gap-fill insulating film formed inside the deep trench isolation. The one or more trench corners is formed in a slanted shape from a top view.

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Patent Owner(s)

Patent OwnerAddress
SK KEYFOUNDRY INCCHEONGJU-SI

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kang, Yang Beom Cheongju-si, KR 15 12
Lee, Sang Uk Cheongju-si, KR 40 189

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