Conductivity reducing features in an integrated circuit

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United States of America Patent

PATENT NO 12205942
APP PUB NO 20220375923A1
SERIAL NO

17374214

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Abstract

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An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.

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Patent Owner(s)

Patent OwnerAddress
NXP B V411 E PLUMERIA DRIVE MS41 SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cong, Feng Shanghai, CN 23 105
Pan, Tingting Shanghai, CN 6 2
Quax, Guido Wouter Willem Wijchen, NL 10 20
Zhu, Dongyong Shanghai, CN 6 14

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