Memory circuit and method of operating same
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United States of America Patent
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Jan 21, 2025
Grant Date -
Dec 21, 2023
app pub date -
Jan 20, 2023
filing date -
Jun 15, 2022
priority date (Note) -
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Abstract
A memory circuit includes a first and a second bit line coupled to a set of memory cells, a local input output circuit including a first and a second data line, a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal, a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal, a switching circuit configured to transfer a first and second input signal to the corresponding first and second data line during a write operation, and to electrically isolate the first and second data line from the first and second input signal during a read operation, and a first latch configured as a sense amplifier, during the read operation, and configured as a write-in latch, during the write operation.
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