Testing of analog neural memory cells in an artificial neural network
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United States of America Patent
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Jan 21, 2025
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Oct 6, 2022
app pub date -
Jun 15, 2022
filing date -
Sep 12, 2019
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Abstract
In one example, a method of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, comprises asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.
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