3D semiconductor memory device and method of fabricating same

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12200936
APP PUB NO 20240057336A1
SERIAL NO

18492504

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Abstract

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A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction.

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Patent Owner(s)

  • SAMSUNG ELECTRONICS CO., LTD.

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Han, Jee Hoon Hwaseong-si, KR 34 100
Kanamori, Kohji Seongnam-si, KR 141 1171
Kang, Seo-Goo Seoul, KR 17 75
Ryu, Hyo Joon Hwaseong-si, KR 11 12

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