Load reduced memory module

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12200860
APP PUB NO 20240276639A1
SERIAL NO

18604133

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Abstract

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The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INCSAN JOSE CA

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh San Jose, US 61 1453
Ware, Frederick A Los Altos Hill, US 803 11661

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