Cascaded phase interpolator topology for quadrature-rate multilevel pulse amplitude modulation data sampling
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United States of America
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Jan 14, 2025
Grant Date -
Jan 2, 2025
app pub date -
Jun 27, 2023
filing date -
Jun 27, 2023
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Abstract
A receiver includes a multi-phase clock generator to generate phases of a clock signal and a global phase interpolator (PI) circuit coupled to the multi-phase clock generator and to clock and data recovery (CDR) circuitry. The global PI circuit generates initial-adjusted phases from the phases of the clock signal based on a control signal received from the CDR circuitry. A first local PI receives the initial-adjusted phases of the clock signal and applies a first fixed phase shift to the initial-adjusted phases to generate first final-adjusted phases of the clock signal that are useable to sample a first level of multiple levels of a pulse-amplitude-modulated (PAM) data stream.
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