Memory device, operation method of memory device, and page buffer included in memory device
Number of patents in Portfolio can not be more than 2000
United States of America
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Jan 14, 2025
Grant Date -
Nov 30, 2023
app pub date -
Aug 15, 2023
filing date -
Aug 15, 2023
priority date (Note) -
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Abstract
Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.
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