Memory system with threaded transaction support
Number of patents in Portfolio can not be more than 2000
United States of America
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Jan 14, 2025
Grant Date -
Apr 4, 2024
app pub date -
Oct 23, 2023
filing date -
Oct 23, 2023
priority date (Note) -
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Abstract
Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.
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