Methods for making semiconductor-based integrated circuits

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United States of America

PATENT NO 12197123
APP PUB NO 20240045322A1
SERIAL NO

18490794

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Abstract

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A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Yu-Hao Hsinchu, TW 61 370
Kuan, Jui-Feng Hsinchu, TW 68 360
Lee, Hui-Yu Hsin-Chu, TW 24 62
Wu, Chien-Te Hsinchu, TW 38 48

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