Methods and apparatus for testing inaccessible interface circuits in a semiconductor device

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12196805
APP PUB NO 20230266385A1
SERIAL NO

18157344

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Abstract

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A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INCCALIFORNIA USA CALIFORNIA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ware, Frederick A Los Altos Hills, US 803 11661

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