Phase lock loop (PLL) synchronization

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United States of America

PATENT NO 12191865
APP PUB NO 20230378960A1
SERIAL NO

18225477

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Abstract

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In an embodiment, an apparatus includes one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal. The apparatus includes phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal.

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Patent Owner(s)

Patent OwnerAddress
STMICROELECTRONICS INTERNATIONAL N VCHEMIN DU CHAMP-DES-FILLES PLAN-LES-OUATES GENEVA 1228

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ghazali, Mostafa Grenoble, FR 6 38
Jacquet, David Francois Vaulnaveys le Haut, FR 13 25
Kahrizi, Masoud Irvine, US 56 385
Tantos, Andras Bellevue, US 19 657

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