Method for operating semiconductor device including multi-gated I/O system

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12191851
APP PUB NO 20230344428A1
SERIAL NO

18218080

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Abstract

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A method of operating a power-on (PO) signal generator (which generates a PO signal and includes a supply-variation sensitivity-reducing (SVSR) load coupled between a first reference voltage and a first node, and a first transistor coupled between the first node and a second reference voltage, the SVSR load including a first resistor coupled between the first reference voltage and a second node, and a second transistor coupled between the second node and the first node, each of a control input of the SVSR load and a gate terminal the first transistor being coupled to a monitored voltage) includes: when the monitored voltage rises above a threshold voltage of the first transistor, turning on the first transistor, and pulling first and second voltages correspondingly on the first and second nodes, a third voltage of the second transistor, and the PO signal down to a logical low value.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Chia-Jung Hsinchu, TW 88 256
Chang, Shih-Peng Hsinchu, TW 5 2
Wu, Shao-Te Hsinchu, TW 4 2

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