Facilitating alignment of stacked chiplets
Number of patents in Portfolio can not be more than 2000
United States of America
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Jan 7, 2025
Grant Date -
Jan 5, 2023
app pub date -
Jul 19, 2022
filing date -
Jul 19, 2022
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Abstract
In certain embodiments, a method for designing a semiconductor device includes generating a 2D design for fabricating chiplets on a substrate. The chiplets are component levels for a multi-chip integrated circuit. The 2D design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The first and second chiplets are adjacent on the substrate. The second layout is a mirror image of the first layout across a reference line shared by the first and second chiplets. The first surfaces of the first and second chiplets are both either top or bottom surfaces. The method further includes generating one or more photomasks according to the design.
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