Memory and operation method thereof
Number of patents in Portfolio can not be more than 2000
United States of America
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Jan 7, 2025
Grant Date -
Mar 30, 2023
app pub date -
Jan 26, 2022
filing date -
Jan 26, 2022
priority date (Note) -
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status (Latency Note)
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Abstract
A memory includes: first to Nth register circuits each suitable for receiving and storing a failure address transferred from a memory controller when a corresponding selection signal of first to Nth selection signals is activated, where N is an integer equal to or greater than 2; first to Nth resource latch circuits suitable for storing first to Nth resource signals indicating availability of the first to Nth register circuits, respectively; and a priority selection circuit suitable for activating, when two or more of the first to Nth resource signals are activated, one of selection signals respectively corresponding to the activated resource signals among the first to Nth selection signals.
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