DRAM retention test method for dynamic error correction

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12190974
APP PUB NO 20230377668A1
SERIAL NO

18138661

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Abstract

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A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

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Patent Owner(s)

  • RAMBUS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh San Jose, US 61 1453
Tsern, Ely Los Altos, US 113 3988
Vogelsang, Thomas Mountain View, US 186 1652
Ware, Frederick A Los Altos Hills, US 803 11661

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