Memory circuit and method of operating the same
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United States of America
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Jan 7, 2025
Grant Date -
Sep 7, 2023
app pub date -
May 12, 2023
filing date -
May 12, 2023
priority date (Note) -
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Abstract
A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.
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