Duty-cycle-correcting clock distribution architecture

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United States of America

PATENT NO 12184300
APP PUB NO 20240120934A1
SERIAL NO

18494731

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Abstract

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Clock and other cyclical signals are driven onto respective capacitively-loaded segments of a distribution path via inverting buffer stages that self-correct for stage-to-stage duty cycle error, yielding a balanced signal duty cycle over the length of the distribution path.

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Patent Owner(s)

Patent OwnerAddress
GIGAJOT TECHNOLOGY INCGLENDALE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Zhang, Dexue Arcadia, US 12 25

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