Configuration of ADC data rates across multiple physical channels
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United States of America
Stats
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Dec 31, 2024
Grant Date -
Jul 27, 2023
app pub date -
Nov 1, 2022
filing date -
Nov 1, 2022
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.
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International Classification(s)
- 2022 Application Filing Year
- H03M Class
- 1388 Applications Filed
- 948 Patents Issued To-Date
- 68.30 % Issued To-Date
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- H03M Class
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