Sub-sampling phase locked loop (SSPLL) with saturated reference feedback
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United States of America
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Dec 31, 2024
Grant Date -
Jan 25, 2024
app pub date -
Jul 19, 2023
filing date -
Jul 19, 2023
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Abstract
A phase locked loop (PLL) includes a phase detector configured to receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency, sample the feedback signal, and output a phase detection signal indicative of a phase of the feedback signal. A voltage controlled oscillator is configured to generate an output signal based on the phase detection signal. The output signal has an output frequency greater than the reference frequency. Feedback circuitry is configured to detect a signal edge of the output signal and selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
THE REGENTS OF THE UNIVERSITY OF MICHIGAN | 1600 HURON PARKWAY 2ND FLOOR OFFICE OF TECHNOLOGY TRANSFER ANN ARBOR MI 48109-2590 |
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- [Patents Count]
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Belz, Matthew R | Columbus, US | 1 | 1 |
Flynn, Michael P | Ann Arbor, US | 27 | 276 |
Jie, Lu | Ann Arbor, US | 2 | 1 |
Song, Seungheun | Ann Arbor, US | 6 | 4 |
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