Latch circuit and memory device
Number of patents in Portfolio can not be more than 2000
United States of America
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Dec 31, 2024
Grant Date -
Nov 23, 2023
app pub date -
Jul 31, 2023
filing date -
Jul 31, 2023
priority date (Note) -
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status (Latency Note)
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Abstract
A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.
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