Self-aligned contacts for thin film transistors

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12183831
APP PUB NO 20200227568A1
SERIAL NO

16638301

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Abstract

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Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATIONSANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chu-Kung, Benjamin Boise, US 218 2483
Dewey, Gilbert Hillsboro, US 450 4629
Kavalieros, Jack T Portland, US 527 8604
Le, Van H Beaverton, US 275 3341
Pillarisetty, Ravi Portland, US 452 8118
Reshotko, Miriam R Portland, US 19 292
Sharma, Abhishek A Hillsboro, US 257 560
Shivaraman, Shriram Hillsboro, US 84 526
Tan, Li Huey Hillsboro, US 8 16
Tronic, Tristan A Aloha, US 39 55

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