System and method for write clock double data rate duty cycle correction

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12183427
SERIAL NO

17967040

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Abstract

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The present disclosure relates to a system and method for duty cycle correction is provided. The method may include receiving a signal at a duty cycle adjuster and performing serializer clock duty cycle correction at the duty cycle adjuster. The method may further include performing true clock duty cycle correction at a transmitter duty cycle adjuster and performing complementary duty cycle distortion correction at the transmitter duty cycle adjuster.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gugwad, Sachin Ramesh Bangalore, IN 8 10
Ravi, Hari Anand Karnataka, IN 10 12

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