Duty cycle correction device for use in cascaded circuits and related large touch and display driver integration system
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United States of America
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Dec 24, 2024
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N/A
app pub date -
Jul 12, 2023
filing date -
Jul 12, 2023
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Abstract
A duty cycle correction device includes: a phase-locked Loop (PLL)-based duty cycle correction circuit, a bypass duty cycle correction circuit and a multiplexer. The PLL-based duty cycle correction circuit is configured to receive and correct an input clock signal to generate a PLL-based corrected signal. The bypass duty cycle correction circuit is configured to be clocked by the input clock signal to sample a logic signal at its input terminal to generate a bypass corrected signal. The multiplexer is coupled to the PLL-based duty cycle correction circuit and the bypass duty cycle correction circuit and is configured to select one of the PLL-based corrected signal, the bypass corrected signal and the input clock signal as an output clock signal.
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