Integrated circuits employing always-on watchdog timer for providing regular power reset
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United States of America
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Dec 24, 2024
Grant Date -
Apr 11, 2024
app pub date -
May 23, 2023
filing date -
May 23, 2023
priority date (Note) -
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Abstract
An integrated circuit includes a power-on reset (POR) circuit, a watchdog timer, a first AND gate and a power management control circuit. The POR circuit is used to receive an input voltage to generate a POR signal and generate a clock signal. The watchdog timer is used to generate a timeout signal according to the clock signal when the POR signal has an enabling voltage, the clock signal enabling generation of timeout pulses in the timeout signal at predetermined time intervals. The first AND gate including a first input terminal for receiving the POR signal; a second input terminal for receiving the timeout signal; and an output terminal for outputting a reset signal according to the POR signal and the timeout signal. The power management control circuit is used to reset an output current in response to a reset pulse in the reset signal.
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