Apparatus and methods for reducing latencies associated with link state transitions within die interconnect architectures
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
Dec 24, 2024
Grant Date -
N/A
app pub date -
Jun 21, 2023
filing date -
Jun 21, 2023
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully