Uniform layouts for SRAM and register file bit cells
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United States of America
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Dec 17, 2024
Grant Date -
Oct 12, 2023
app pub date -
Jun 14, 2023
filing date -
Jun 14, 2023
priority date (Note) -
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Abstract
Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.
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