Semiconductor package and method of fabricating the same
Number of patents in Portfolio can not be more than 2000
United States of America
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Dec 17, 2024
Grant Date -
Mar 2, 2023
app pub date -
Apr 7, 2022
filing date -
Apr 7, 2022
priority date (Note) -
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Abstract
A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.
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