Digital-to-analog converter glitch reduction techniques
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
Dec 10, 2024
Grant Date -
Jun 27, 2024
app pub date -
Dec 21, 2022
filing date -
Dec 21, 2022
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A digital technique to reduce or minimize switching in a DAC by using a partial DAC data ignore switching mode. In the partial DAC data ignore switching mode, a control circuit compares first and second data, such a first and second digital words, and operates corresponding switches only when the first data differ from the second data. The techniques are applicable to many types of DACs, including voltage output DACs, current output DACs, variable resistance DACs, digital rheostats, digital potentiometers, digiPOTs.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully