Modified control loop in a digital phase-locked loop
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United States of America
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Dec 10, 2024
Grant Date -
Jun 22, 2023
app pub date -
Dec 21, 2022
filing date -
Dec 21, 2022
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Abstract
A method for generating a clock signal using a digital phase-locked loop includes updating a gain of a variable gain digital filter of the digital phase-locked loop using an estimate error of a current estimate of a phase and a frequency of an input clock signal and a measurement error of a measurement of the phase and the frequency of the input clock signal. The gain may include a proportional gain component and an integral gain component. The method may include calculating the current estimate of the phase and the frequency of the input clock signal based on a previous estimate of the phase and the frequency of the input clock signal, the measurement of the phase and the frequency of the input clock signal, and the gain of the variable gain digital filter. The gain may be updated every cycle of the input clock signal.
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