3D semiconductor package with die-mounted voltage regulator

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12165981
APP PUB NO 20230197619A1
SERIAL NO

17556346

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Abstract

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A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

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Patent Owner(s)

Patent OwnerAddress
ADVANCED MICRO DEVICES INC2485 AUGUSTINE DRIVE SANTA CLARA CA 95054

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Agarwal, Rahul Santa Clara, US 183 1209
Loh, Gabriel H Santa Clara, US 138 2229
Swaminathan, Raja Santa Clara, US 31 17
Wilkerson, Brett P Santa Clara, US 35 155

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