Dual loop voltage regulator

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12164319
SERIAL NO

17128073

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Abstract

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A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Burton, Edward Hillsboro, US 29 371
Pasdast, Gerald San Jose, US 43 167
Tiagaraj, Sathya Narasimman Santa Clara, US 12 10

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