Layout structure with minimal additional parasitic capacitance

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12159864
APP PUB NO 20220165723A1
SERIAL NO

17525966

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Abstract

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Provided is a layout structure adapted for a signal format converter. The layout structure includes a first and a second capacitor array. The first capacitor array is disposed on one side of a reference axis, and includes multiple first capacitor units that form multiple first capacitors. The first capacitors respectively have multiple first capacitances. The second capacitor array is disposed on the other side of the reference axis, and includes multiple second capacitor units that form multiple second capacitors. The second capacitors respectively have multiple second capacitances. The first capacitors respectively correspond to the second capacitors. Each first capacitor and each corresponding second capacitor are symmetrical with respect to the reference axis, or each first capacitor and each corresponding second capacitor are separated from each other by the same distance. Each first capacitor and each corresponding second capacitor have the same capacitance.

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Patent Owner(s)

Patent OwnerAddress
ALI CORPORATION6F NO 1 JINSHAN 8TH ST HSINCHU 300

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lan, Tzu-Wei Taipei, TW 3 6
Lin, Wei-Jian Taipei, TW 2 4

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