Computational memory with cooperation among rows of processing elements and memory thereof
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United States of America
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Nov 19, 2024
Grant Date -
Nov 16, 2023
app pub date -
Jul 20, 2023
filing date -
Jul 20, 2023
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Abstract
A computing device includes an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations, memory cells connected to each processing element to store data related to the SIMD operations, and a cache connected to each processing element to cache data related to the SIMD operations. Caches of adjacent processing elements are connected. The same or another computing device includes rows of mutually connected processing elements to share data. The computing device further includes a row arithmetic logic unit (ALU) at each row of processing elements. The row ALU of a respective row is configured to perform an operation with processing elements of the respective row.
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