Method of fabricating a semiconductor layout and a semiconductor structure

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12147156
APP PUB NO 20230138898A1
SERIAL NO

17555532

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Abstract

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The present disclosure discloses a method of fabricating a semiconductor layout comprising the following steps. A layout is provided, and the layout includes a plurality of connection patterns. The connection patterns are decomposed to a plurality of first connection patterns and a plurality of second connection patterns alternatively arranged with each other. An optical proximity correction process is performed on the first connection patterns and the second connection patterns to form a plurality of third connection patterns and a plurality of fourth connection patterns, wherein at least a portion of the third connection patterns is overlapped with the fourth connection patterns. The third connection patterns and the fourth connection patterns are outputted to form photomasks. Accordingly, the quality of the photomask may be improved, and the photomask may therefore include more accurate patterns and contours. The present disclosure also provides a method of fabricating a semiconductor structure.

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Patent Owner(s)

Patent OwnerAddress
FUJIAN JINHUA INTEGRATED CIRCUIT CO LTDNO 88 LIANHUA AVENUE INTEGRATED CIRCUIT SCIENCE PARK JINJIANG CITY QUANZHOU CITY FUJIAN PROVINCE 362200 QUANZHOU CITY FUJIAN PROVINCE 362200

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Li, Wenzhang Quanzhou, CN 1 0
Yan, Yifei Quanzhou, CN 27 5

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